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1 ISL8013A 3a low quiescent current 1mhz high efficiency synchronous buck regulator ISL8013A the ISL8013A is a high efficiency, monolithic, synchronous step-down dc/dc converter that can deliver up to 3a continuous output current from a 2.8v to 5.5v input supply. it uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the ISL8013A integrates a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 300mv dropout voltage at 3a output current. high 1mhz pulse-width modulation (pwm) switching frequency allows the use of small external components and sync input enables multiple ics to synchronize out of phase to reduce ripple and eliminate beat frequencies. the ISL8013A can be configured for discontinuous or forced continuous operation at light load. forced continuous operation reduces noise and rf interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. fault protection is provided by internal hiccup mode current limiting during short circuit and overcurrent conditions, an output over voltage comparator and over-temperature monitor circuit. a power good output voltage monitor indicates when the output is in regulation. the ISL8013A is offered in a space saving 4x4 qfn lead free package with exposed pad lead frames for low thermal resistance. the ISL8013A includes a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 300mv dropout voltage at 3a. the ISL8013A offers a 1ms power good (pg) timer at power-up. when shutdown, ISL8013A discharges the output capacitor. other features include internal soft-start, internal compensation, overcurrent protection, and thermal shutdown. the ISL8013A is offered in a 4mmx4mm 16 ld qfn package with 1mm maximum height. the complete converter occupies less than 0.4in 2 area. features ? high efficiency synchronous buck regulator with up to 97% efficiency ? power-good (pg) output with a 1ms delay ? 2.8v to 5.5v supply voltage ? 3% output accuracy over-temperature/load/line ? 3a output current ? start-up with pre-biased output ? internal soft-start - 1ms ? soft-stop output discharge during disabled ? 35a quiescent supply current in pfm mode ? selectable forced pwm mode and pfm mode ? external synchronization up to 4mhz ? less than 1a logic controlled shutdown current ? 100% maximum duty cycle ? internal current mode compensation ? peak current limiting and hiccup mode short circuit protection ? over-temperature protection ? small 16 ld 4mmx4mm qfn ? pb-free (rohs compliant) applications* (see page 16) ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems ? li-ion battery powered devices ? small form factor (sfp) modules ? bar code readers caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. november 25, 2009 fn7526.0
2 fn7526.0 november 25, 2009 pin configuration ISL8013A (16 ld qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8013Airz 80 13airz -40 to +85 16 ld 4x4 qfn l16.4x4 notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for ISL8013A . for more information on msl please see techbrief tb363 . 1 3 4 15 vin vin vdd synch nc lx lx lx 16 14 13 2 12 10 9 11 6 578 pgnd pgnd sgnd sgnd en nc pg vfb refer to application note an1365 for more layout suggestions. pin descriptions pin number pin name description 1, 2 vin input supply voltage. connect a 10 f ceramic capacitor to power ground. 3 vdd input supply voltage for the anal og circuitry. connect to vin pin. 5 en regulator enable pin. enable the output when driven to high. shut down the chip and discharge output capacitor wh en driven to low. do not leave this pin floating. 7 pg 1ms timer output. at power-up or en hi, this output is a 1ms dela yed power-good signal for the output voltage. 4 synch mode selection pin. conn ect to logic high or input vo ltage vdd for pwm mode. connect to logic low or ground for pfm mode. connec t to an external f unction generator for synchronization with the negative edge tr igger. do not leave this pin floating. 13, 14, 15 lx switching node connection. connect to one terminal of the inductor. 11, 12 pgnd power ground 9, 10 sgnd signal ground. 8 vfb buck regulator output feedback. connect to the output through a resistor divider for adjustable output voltage. fo r 0.8v output voltage, conne ct this pin to the output. 6, 16 nc no connect. - exposed pad the exposed pad must be connected to the sgnd pin for proper electrical performance. place as much vias as poss ible under the pad connecting to sgnd plane for optimal thermal performance. ISL8013A
3 fn7526.0 november 25, 2009 typical application figure 1. typical application diagram l 1.5h lx pgnd vfb vin en pg synch input 2.8v to 5.5v output 1.8v c1 2 x 22f ISL8013A c2 r2 124k r3 100k 2 x 22f vdd sgnd c3 47pf r1 100k ISL8013A
4 fn7526.0 november 25, 2009 block diagram figure 2. functional block diagram lx + + csa + + ocp 1.4v 0.5v skip + + + slope comp slope soft start soft 0.8v eamp comp pwm/pfm logic controller protection driver vfb + 0.736v pg synch shutdown vin pgnd oscillator zero-cross sensing bandgap scp + 0.2v en shutdown 1ms delay 27pf 390k sgnd 3pf 6k - - - - - - - - ISL8013A
5 fn7526.0 november 25, 2009 absolute maximum ratings ( reference to gnd ) thermal information vin, vdd . . . . . . . . . . . . . . -0.3v to 6v (dc) or 7v (20ms) en, synch, pg . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v lx . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.8v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . 2.8v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . 0a to 3a ambient temperature range . . . . . . . . . . . . -40c to +85c thermal resistance (typical, notes 4, 5)) ja (c/w) jc (c/w) 16 ld 4x4 qfn package . . . . . . . 39 3 junction temperature range . . . . . . . . . . -55c to +125c storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits are establ ished over the recommended operating conditions and the typical specificat ion are measured at the following conditions unless otherwise noted: t a = -40c to +85c, v in = 3.6v, en = vdd. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ max (note 7) units input supply v in undervoltage lockout threshold v uvlo rising, no load - 2.6 2.8 v falling, no load 2.15 2.35 - v quiescent supply current i vin synch = gnd, no load at the output - 35 - a synch = gnd, no load at the output and no switches switching - 30 45 a synch = vdd, f s = 1mhz, no load at the output - 6.5 10 ma shut down supply current i sd v in = 5.5v, en = low - 0.1 2 a output regulation reference voltage v ref 0.790 0.8 0.810 v vfb bias current i vfb vfb = 0.75v - 0.1 - a line regulation v in = v o + 0.5v to 5.5v (minimal 2.8v) - 0.2 - %/v soft-start ramp time cycle - 1 - ms overcurrent protection current limit blanking time t ocon - 17 - clock pulses overcurrent and auto restart period t ocoff - 4 - ss cycle switch current limit i limit (note 6) 4.0 4.8 5.9 a peak skip limit i skip (note 6) - 1.2 - a compensation error amplifier trans-conductance - 20 - a/v trans-resistance rt 0.213 0.25 0.287 ISL8013A
6 fn7526.0 november 25, 2009 lx p-channel mosfet on-resistance v in = 5v, i o = 200ma - 50 75 m v in = 2.8v, i o = 200ma - 70 100 m n-channel mosfet on-resistance v in = 5v, i o = 200ma - 50 75 m v in = 2.8v, i o = 200ma - 70 100 m lx maximum duty cycle - 100 - % pwm switching frequency f s 0.80 1.00 1.20 mhz lx minimum on-time synch = high - - 140 ns pg output low voltage sinking 1ma - - 0.3 v delay time (rising edge) 0.65 1 1.35 ms pg pin leakage current pg = vin = 3.6v - 0.01 0.1 a pgood rising threshold percent age of regulation voltage 89 92 95 % pgood falling threshold percentage of regulation voltage 85 88 91.5 % pgood delay time (falling edge) - 15 - s en, synch logic input low - - 0.4 v logic input high 1.4 - - v synch logic input leakage current i synch pulled up to 5.5v - 0.1 1 a enable logic input leakage current i en - 0.1 1 a thermal shutdown - 140 - c thermal shutdown hysteresis - 25 - c notes: 6. limits established by characterization and are not production tested. 7. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. electrical specifications unless otherwise noted, all parameter limits are establ ished over the recommended operating conditions and the typical specificat ion are measured at the following conditions unless otherwise noted: t a = -40c to +85c, v in = 3.6v, en = vdd. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units ISL8013A
7 fn7526.0 november 25, 2009 ISL8013A typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . figure 3. efficiency vs load (1mhz 3.3 v in pwm) figure 4. efficiency vs load (1mhz 3.3 v in pfm) figure 5. efficiency vs load ( 1mhz 5v in pwm) figure 6. efficiency vs load ( 1mhz 5v in pfm ) figure 7. power dissipation vs load (1mhz, v out = 1.8v) figure 8. power dissipation with no load vs v in (pwm v out = 1.8v) 40 50 60 70 80 90 100 output load (a) efficiency (%) 2.5v out-pwm 1.8v out-pwm 1.5v out-pwm 1.2v out-pwm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) 2.5v out-pfm 1.8v out-pfm 1.5v out-pfm 1.2v out-pfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 40 50 60 70 80 90 100 output load (a) efficiency (%) 2.5v out-pwm 1.8v out-pwm 1.5v out-pwm 1.2v out-pwm 3.3v out-pwm 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output load (a) efficiency (%) 2.5v out-pfm 1.8vout-pfm 1.5v out-pfm 1.2v out-pfm 3.3v out-pfm 0.0 0.5 1.0 1.5 2.0 2.5 3. 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) power dissipation (mw) 5v in-pwm 3 . 3 v i n - p f m 3.3v in-pwm 5v in-pfm 0 25 50 75 100 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) power dissipation (mw)
8 fn7526.0 november 25, 2009 figure 9. power dissipation with no load vs v in (pfm v out = 1.8v) figure 10. v out regulation vs load (1mhz, v out = 1.2v) figure 11. v out regulation vs load (1mhz, v out = 1.5v) figure 12. v out regulation vs load (1mhz, v out = 1.8v) figure 13. v out regulation vs load (1mhz, v out = 2.5v) figure 14. v out regulation vs load (1mhz, v out = 3.3v) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . (continued) 0 0.05 0.10 0.15 0.20 0.25 power dissipation (mw) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) 0.0 0.5 1.0 1.5 2.0 2.5 3. 0 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 output load (a) output voltage (v) 5v in-pwm 5v in-pfm 3.3v in-pfm 3.3v in-pwm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 output load (a) output voltage (v) 5v in-pwm 5v in-pfm 3.3v in-pfm 3.3v in-pwm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 output load (a) output voltage (v) 5v in-pwm 5v in-pfm 3.3v in-pwm 3.3v in-pfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 output load (a) output voltage (v) 5v in-pwm 5v in-pfm 3.3v in-pwm 3.3v in-pfm 0.0 0.5 1.0 1.5 2.0 2.5 3. 0 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 output load (a) output voltage (v) 5v in-pwm 5v in-pfm 4.5v in-pfm 4.5v in-pwm ISL8013A
9 fn7526.0 november 25, 2009 figure 15. output voltage regulation vs vin (pwm v out = 1.8 ) figure 16. output voltage regulation vs vin (pfm v out = 1.8v) figure 17. steady state operation at no load (pwm) figure 18. steady state operation at no load (pfm) figure 19. steady state operation with full load figure 20. mode transition ccm to dcm typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . (continued) 1.750 1.760 1.770 1.780 1.790 1.800 1.810 1.820 1.830 output voltage (v) 2.02.53.03.54.04.55.05. 5 input voltage (v) 3a load pwm 0a load pwm 1.750 1.760 1.770 1.780 1.790 1.800 1.810 1.820 1.830 output voltage (v) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5 input voltage (v) 3a load 0a load lx 2v/div v out ripple 20mv/div il 0.5a/div lx 2v/div v out ripple 20mv/div il 0.5a/div lx 2v/div v out ripple 20mv/div il 1a/div lx 2v/div v out ripple 50mv/div il 1a/div ISL8013A
10 fn7526.0 november 25, 2009 figure 21. mode transition dcm to ccm figure 22. load transient (pwm) figure 23. load transient (pfm) figure 24. soft-start with no load (pwm) figure 25. soft-start at no load (pfm) figure 26. soft-start with pre-biased 1v typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . (continued) lx 2v/div v out ripple 50mv/div il 1a/div v out ripple 50mv/div il 1a/div lx 2v/div v out ripple 50mv/div il 1a/div en 5v/div v out 0.5v/div il 1a/div pg 5v/div en 5v/div v out 0.5v/div il 1a/div pg 5v/div en 5v/div v out 0.5v/div il 5a/div pg 5v/div ISL8013A
11 fn7526.0 november 25, 2009 figure 27. soft-start at full load figure 28. soft-discharge shutdown figure 29. steady state operation at no load with frequency = 2mhz figure 30. steady state operation at full load with frequency = 2mhz figure 31. steady state operation at no load with frequency = 4mhz figure 32. steady state operation at full load (pwm) with frequency = 4mhz typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . (continued) v out 0.5v/div il 1a/div en 5v/div pg 5v/div v out 0.5v/div il 1a/div en 5v/div pg 5v/div lx 2v/div synch 2v/div v out ripple 20mv/div il 1a/div lx 2v/div synch 2v/div v out ripple 20mv/div il 1a/div lx 2v/div synch 2v/div v out ripple 20mv/div il 1a/div lx 2v/div synch 2v/div v out ripple 20mv/div il 1a/div ISL8013A
12 fn7526.0 november 25, 2009 theory of operation the ISL8013A is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at 1mhz fixed switching frequency under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 35a. the supply current is typically only 0.1a when the regulator is shut down. pwm control scheme pulling the synch pin hi (>2. 5v) forces the converter into pwm mode, regardless of output current. the ISL8013A employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting. figure 2 shows the block diagram. the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the gain for the current sensing circuit is typically 250mv/a. the control refere nce for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosf et is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa and the slope compensation (237mv/s) reaches the control referenc e of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 36 shows the typical operating waveforms during the pwm op eration. the dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start figure 33. output short circuit figure 34. output short circuit recovery figure 35. output current limit vs temperature typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , synch = 0v, l = 1.5h, c 1 = 2x22f, c 2 = 2x22f, i out = 0a to 3a . (continued) phase 2v/div v out 0.5v/div il 2a/div pg 5v/div lx 2v/div v out 1v/div il 2a/div pg 5v/div 4.000 4.125 4.250 4.375 4.500 4.625 4.750 4.875 5.000 -50-250 255075100 temperature (c) output current (a) ocp_3.3v in ocp_5v in ISL8013A
13 fn7526.0 november 25, 2009 block, only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 390k rc network. the maximum eamp voltage output is precisely clamped to 1.6v. skip mode pulling the synch pin lo (<0. 4v) forces the converter into pfm mode. the ISL8013A enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 37 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 2 monitors the n-mosfet current for zero crossing. when 8 consecutive cycles of the inductor current crossing zero are de tected, the regulator enters the skip mode. during the eight detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 2. each pulse cycle is still synchronized by the pwm clock. the p-mosfet is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. then the inductor current is discharging to 0a and stays at zero. the internal clock is disabled.the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be turned on again at the rising edge of the internal clock as it repeats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. synchronization control the frequency of operation can be synchronized up to 4mhz by an external signal applied to the synch pin. the falling edge on the synch triggers the rising edge of the lx pulse. make sure that the minimum on time of the lx node is greater than 140ns. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 2. the current sensing circuit has a gain of 250mv/a, from the p-mosfet current to the csa output. when the csa output reaches 1.4v, which is equivalent to 4.8a for the switch current, the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurren t function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the ne xt switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulator will be shut down under an overcurrent fault condition. an overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of four soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. if the overcurrent condition goes away during the delay of four soft-start periods, the output will resume back into regulation point after hiccup mode expires. short-circuit protection the short-circuit protection scp comparator monitors the vfb pin voltage for output short-circuit protection. when the vfb is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start- up or an output short-circuit event. figure 36. pwm operation waveforms v eamp v csa duty cycle i l v out ISL8013A
14 fn7526.0 november 25, 2009 . pg during power-up, the open-drain power good output holds low for about 1ms after v out reaches the regulation voltage. the pg output also serves as a 1ms delayed the power good signal when the pull-up resistor r 1 is installed. uvlo when the input voltage is below the undervoltage lock-out (uvlo) threshold, the regulator is disabled. soft start-up the soft-start-up reduces the inrush current during the start-up. the soft-start block outputs a ramp reference to the input of the error amplifie r. this voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. when vfb is less than 0.2v at the beginning of the soft-start, the switching frequency is reduced to 1/3 of the nominal value so that the output can start-up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support pre-biased output condition. enable the enable (en) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft-start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs or the v in uvlo is set, the outputs discharge to gnd through an internal 100 switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 50m and the on-resistance for the n-mosfet is typically 50m . 100% duty cycle the ISL8013A features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL8013A can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shut-down the ISL8013A has built-in thermal protection. when the internal temperature reaches +140c, the regulator is completely shut down. as the temperature drops to +115c, the ISL8013A resumes operation by stepping through the soft-start. applications information output inductor and capacitor selection to consider steady state and transient operations, ISL8013A typically uses a 1.5h output inductor. the higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. it is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. the inductor ripple current can be expressed as shown in equation 1: the inductor?s saturation current rating needs to be at least larger than the peak current. the ISL8013A protects the typical peak cu rrent 4.8a. the saturation current needs be over 5.5a for maximum output current application. ISL8013A uses internal co mpensation network and the output capacitor value is dependent on the output figure 37. skip mode operation waveforms clock i l v out nominal +1.5% nominal pfm current limit load currentt 0 pwm pfm 8 cycles i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? ------------------------------------- = (eq. 1) ISL8013A
15 fn7526.0 november 25, 2009 voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended x5r or x7r minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable. additional output capacitance should be added for better pe rformances in applications where high load transient or lo w output ripple is required. it is recommended to check the system level performance along with the simulation model. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to figure 1. the output voltage programming resistor, r 3 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k , as shown in equation 2. if the output voltage desired is 0.8v, then r 3 is left unpopulated and r 2 is shorted. there is a leakage current from vin to lx. it is recommended to preload the output with 10a minimum. for better performance, add 47pf in parallel with r 2 (100k ). input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. two 22f x5r or x7r ceramic capacitors are a good starting point for the input capacitor selection. table 1. output capacitor value vs v out v out (v) c out (f) l (h) 0.8 2 x 22 1.0~2.2 1.2 2 x 22 1.0~2.2 1.5 2 x 22 1.5~3.3 1.8 2 x 22 1.5~3.3 2.5 2 x 22 1.5~3.3 3.3 2 x 22 2.2~4.7 3.6 2 x 22 2.2~4.7 r 3 r 2 0.8v ? v out 0.8v ? ---------------------------------- = (eq. 2) ISL8013A
16 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7526.0 november 25, 2009 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL8013A to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 11/25/09 fn7526.0 initial release. ISL8013A
17 fn7526.0 november 25, 2009 ISL8013A package outline drawing l16.4x4 16 lead quad flat no-lead plastic package rev 6, 02/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view index area (4x) 0.15 pin 1 6 4.00 4.00 a b +0.15 -0.10 16x 0 . 60 2 . 10 0 . 15 0.28 +0.07 / -0.05 pin #1 index area 5 8 4 0.10 c m 12 9 4 0.65 12x 13 4x 1.95 16 1 6 a b ( 3 . 6 typ ) ( 2 . 10 ) ( 12x 0 . 65 ) ( 16x 0 . 28 ) ( 16 x 0 . 8 ) see detail "x" base plane 1.00 max 0 . 2 ref 0 . 00 min. 0 . 05 max. c 5 0.08 c c seating plane 0.10 c

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